Details of CS2101 (Autumn 2026)
| Level: 2 | Type: Theory | Credits: 4.0 |
| Course Code | Course Name | Instructor(s) |
|---|---|---|
| CS2101 | Computer Organizations and Architecture | _ Not Yet Decided _ |
| Preamble |
|---|
| Course Objective
To provide fundamental understanding of computer hardware organization, instruction execution, memory hierarchy, I/O systems, and performance enhancement techniques, bridging digital design and computer architecture. Course Outcomes After completing this course, students will be able to: Understand internal working of a computer system Design basic datapath and control units Analyze instruction execution and performance Understand memory hierarchy and cache design Interface I/O subsystems effectively |
| Syllabus |
|---|
| Module 1: Introduction to Computer Systems
Function and structure of a computer Basic functional blocks: CPU, Memory, I/O subsystems Interconnection of components Performance metrics: throughput, latency, speedup Evolution of computer architectures Module 2: Data Representation & Computer Arithmetic Number systems and data representation - Unsigned and signed integers - Sign-magnitude, 1s complement, 2s complement - Fixed-point and floating-point representation (IEEE 754) Arithmetic circuits and algorithms - Adders: Ripple-carry, Carry-lookahead - Subtraction techniques - Multiplication: Shift-and-add, Booth algorithm, Carry-save multipliers - Division: Restoring and non-restoring division - Floating-point arithmetic Module 3: Instruction Set Architecture (ISA) Machine instructions and operands Instruction formats and instruction cycles Addressing modes Instruction sets: CISC vs RISC RTL interpretation of instructions Case studies of common processor ISAs Module 4: CPU Organization & Control Unit Processor organization: Registers, ALU, Control Unit Datapath design and CPU buses Instruction execution cycle Control unit design: - Hardwired control - Microprogrammed control External CPU interfaces Case study: Simple hypothetical CPU design Module 5: Pipelining and Advanced Processing Basic concepts of pipelining Pipeline performance: throughput and speedup Pipeline hazards and solutions Introduction to multiprocessors and multicore systems Overview of modern processor examples Module 6: Memory Subsystem & Hierarchy Semiconductor memory technologies: SRAM, DRAM, ROM, Flash Memory organization and interleaving Error detection and correction Cache memory: - Cache organization and hierarchy - Mapping techniques - Replacement policies - Write policies - Cache coherence basics Virtual memory and Memory Management Unit (MMU) On-chip vs off-chip memory performance Module 7: Input/Output Subsystem I/O organization and interfaces Program-controlled I/O Interrupt-driven I/O DMA-based I/O I/O buses: PCI, USB, SCSI (overview) Synchronous vs asynchronous I/O Peripheral devices: keyboard, display, storage devices |
| References |
|---|
| Suggested Textbooks
1. Patterson ; Hennessy Computer Organization and Design 2. William Stallings Computer Organization and Architecture 3. Hamacher, Vranesic & Zaky Computer Organization 4. Andrew Tanenbaum Structured Computer Organization 5. Berhooz Parhami Computer Architecture 6. Jean-Loup Baer Microprocessor Architecture |
Course Credit Options
| Sl. No. | Programme | Semester No | Course Choice |
|---|---|---|---|
| 1 | IP | 1 | Not Allowed |
| 2 | IP | 3 | Not Allowed |
| 3 | MP | 1 | Not Allowed |
| 4 | MP | 3 | Not Allowed |
| 5 | MR | 1 | Elective |
| 6 | MR | 3 | Not Allowed |
| 7 | MS ( Computational and Data Sciences ) | 3 | Core |
| 8 | MS | 5 | Elective |
| 9 | MS | 7 | Elective |
| 10 | MS | 9 | Elective |
| 11 | RS | 1 | Not Allowed |
| 12 | RS | 2 | Not Allowed |